The VLSI/Nanoelectronic Circuit Design Group

Nanoscale Electronic Circuits and Architectures

The infant field of molecular nanoelectronics is often defined as including any technology whose feature sizes are on the scale of single molecules. Many in the field have performed experiments that have shown how such devices could be fabricated with useful properties such recitification, hysteresis, and negative differential resistance (NDR). Our work in this regard focuses on the uses of such devices for the implementation of digital logic and memory -- we are quite literally exploring ways of building computers from organic molecules. To date, our research has led to low-level design techniques for implementing molecular electronic circuits. Our circuit-level approach (taking actual experimental data to build up device models) has led to molecular electronic PLA circuits, specifically what we call the programmable majority logic array (PMLA) based on NDR.

Hybrid CMOS/Nanoelectronic Logic and Memory

With the emergence of novel nanotechnologies such as self-assembled molecular electronics, a great deal of excitement has been generated over the prospects of future VLSI technology. As exciting as these various nanoscale technologies may be CMOS (i.e., conventional IC technology) is likely to remain the major cornerstone of VLSI for some time due to the vast fabrication infrastructure already in existance. That said, there are major roadblocks ahead and nanotechnology provides many opportunities for overcoming the hurdles. Thus, the approach we are taking is in determining ways in which novel nanotechnologies (e.g., molecular electronics) can be integrated with CMOS to achieve systems that take advantage of the best each technology has to offer. This work has resulted in several important steps toward implementing such hybrid CMOS/Nano circuits where the interface issues are considered from a low level in order to reduce failure rates once the circuits are fabricated. Though our contributions are primarily on the design end, we are actively working with other research groups in actually developing these circuits that we feel offer great potential for the future of VLSI technology.

As part of a greater effort at Polytechnic University to develop new high performance computing (HPC) architectures, our group is also involved in VLSI circuit and system research for multiprocessor systems-on-chips (MPSoC). In a sense, an MPSoC can be thought of as a "supercomputer on a chip" with many processors interconnected on one silicon chip for high performance parallel processing. Efforts in this area are certainly not limited to our group and are in fact part of a trend that can already be seen in the leading microprocessors on the market today. For example, Intel has recently come out with a quad core processor and is moving toward adding more cores in the future. Our research is interested in ways of integrating many cores (80 - 100) on a single chip and exploring ways of ensuring that this can be accomplished for maximum performance, low-power and temperature-aware operation. To this end, one major aspect of this work is on the type of network-on-chip (NoC) that is implemented. In a parallel processor, the network is an integral part of the overall computer architecture and great consideration must be taken to optimize for efficient performance. Our specific efforts include developing a temperature-aware NoC, high performance arbitration, as well as MPSoC architecture for efficient, low-power operation.