The VLSI/Nanoelectronic Circuit Design Group

G. S. Rose, M. R. Stan, and M. M. Ziegler, "A Universal Device Model for Simulating Nanoelectronic Circuits," in Emerging Brain-Inspired Nano-Architectures, V. Beiu and U. Ruckert, Ed., World Scientific, in press.

M. R. Stan, G. S. Rose, and M. M. Ziegler, "Hybrid CMOS/Molecular Integrated Circuits," in Moore’s Law: Beyond Planar Silicon CMOS and into the Nano Era, H. Huff, Ed. Springer,
2008.

G. S. Rose and M. R. Stan, "A Programmable Majority Logic Array using Molecular Scale Electronics," IEEE Trans. Circuits Syst. I, vol. 54, no. 11, pp. 2380-2390, November 2007.

S. Das, A. J. Gates, H. A. Abdu, G. S. Rose, C. A. Picconatto and J. C. Ellenbogen, "Designs for Ultra-Tiny, Special-Purpose Nanoelectronic Circuits," IEEE Trans. Circuits Syst. I, vol. 54, no. 11, pp. 2528-2540, November 2007.

G. S. Rose, Y. Yao, J. M. Tour, A. C. Cabe, N. Gergel-Hackett, N. Majumdar, J. C. Bean,
L. R. Harriott, and M. R. Stan, "Designing CMOS/Molecular Memories while Considering
Device Parameter Variations," ACM Journal of Emerging Technologies in Computing
Systems, vol. 3, no. 1, April 2007.

S. Das, C. A. Picconatto, G. S. Rose, M. M. Ziegler, and J. C. Ellenbogen, "System-Level
Design and Simulation of Nanomemories and Nanoprocessors," in CRC Handbook on Nano
and Molecular Electronics, S. Lyshevski, Ed., CRC, May 2007.

S. Das, G. S. Rose, M. M. Ziegler, C. A. Picconatto, and J. C. Ellenbogen, "Architectures and Simulations for Nanoprocessor Systems Integrated on the Molecular Scale," in Introducing Molecular Electronics, G. Cuniberti, G. Fagas, and K. Richter, Eds. Berlin: Springer, 2005.

G. S. Rose, M. M. Ziegler, and M. R. Stan, "A Large-Signal Universal Device Model for Nanoelectronic Circuit Simulation," IEEE Transactions on Very Large Scale Integration,
vol. 12, no. 11, pp. 1201–1208, Nov. 2004.

H. Manem and G. S. Rose, "The Effect of Device Parameter Variation on Programmable Majority Logic Arrays," in Proceedings of the IEEE Conference on Nanotechnology, Arlington, Texas, August 2008.

H. Manem and G. S. Rose, "The Effects of Logic Partitioning in a Majority Logic Based CMOS-Nano FPGA," poster, IEEE/ACM International Symposium on Nanoscale Architectures, Anaheim, CA, June 2008.

N. Gergel-Hackett, A.A. Hill, C.A. Hacker, C.A. Richter, P. Paliwoda, and G.S. Rose, "The Design, Simulation, and Fabrication of a Hybrid Molecular Electronic Device/CMOS Circuit," Materials Research Society Spring Meeting, San Francisco, CA, March, 2008.

H. Manem, P. C. Paliwoda, and G. S. Rose, "A Hybrid CMOS/Nano FPGA Architecture built from Programmable Majority Logic Arrays," in Proceedings of the ACM Great Lakes Symposium on VLSI, Orlando, Florida, May 2008.

P. C. Paliwoda, D. S. Maragal, and G. S. Rose, "Testing Molecular Devices in CMOS/Nano Integrated Circuits," in Proceedings of the IEEE Conference on Nanotechnology, Hong Kong, China, August 2007, pp. 773-777.

A. C. Cabe, G. S. Rose, and M. R. Stan "Data Encoding Eliminates Parasitic Current Paths in Molecular Memory," in Proceedings of the IEEE Conference on Nanotechnology, Hong Kong, China, August, 2007, pp. 70-75.

N. Gergel-Hackett, G. S. Rose, P. Paliwoda, C. A. Hacker, and C. A. Richter, "On-Chip Characterization of Molecular Electronic Devices: The Design and Simulation of a Hybrid Circuit Based on Experimental Molecular Electronic Device Results," in Proceedings of the ACM Great Lakes Symposium on VLSI, Stresa, Italy, March, 2007.

Z. Qi, W. Huang, A. Cabe, W. Wu, Y. Zhang, G. Rose, and M. R. Stan, "A Design Methodology for a Low-Power, Temperature-Aware SoC Developed for Medical Image Processors," in Proceedings of the 2006 IEEE International SOC Conference, Austin, TX, September, 2006.

A. C. Cabe, Z. Qi, W. Huang, Y. Zhang, M. R. Stan, and G. S. Rose, "A Flexible, Technology Adaptive Memory Generation Tool," in CDNLive! Silicon Valley 2006 Conference
Proceedings, San Jose, CA, September, 2006.

G. S. Rose, A. C. Cabe, N. Gergel-Hackett, N. Majumdar, M. R. Stan, J. C. Bean, L. R.
Harriott, Y. Yao, and J. M. Tour, "Design Approaches for Hybrid CMOS/Molecular Memory Based on Experimental Device Data," in Proceedings of the ACM Great Lakes Symposium
on VLSI, Philadelphia, PA, May 2006, pp. 2-7. (Best Student Paper)

G. S. Rose and M. R. Stan, "A Programmable Majority Logic Array using Molecular Scale Electronics," poster, Fourteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey, CA, February, 2006.

M. R. Stan, G. S. Rose, and M. M. Ziegler, "Hybrid CMOS/molecular Electronic Circuits," in Proceedings of the International Conference on VLSI Design, Hyderabad, India, Jan. 2006.

G. S. Rose and M. R. Stan, "Programmable Logic Using Molecular Devices in a Three
Dimensional Architechture," Molecular-Scale Electronics VII, San Diego, CA, January, 2005.

G. S. Rose and M. R. Stan, "Memory Arrays Based on Molecular RTD Devices," in
Proceedings of the 3rd IEEE Conference on Nanotechnology, San Francisco, CA, August 2003, pp. 453-456.

M. M. Ziegler, G. S. Rose, and M. R. Stan, "A Universal Device Model for Nanoelectronic
Circuit Simulation," in Proceedings of the 2nd IEEE Conference on Nanotechnology, Washington, D.C., August 2002, pp. 83–88.