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Patents

  1. "Methods and apparatus for handling time stamp aging"
    patent no. 6,081,507, June 2000
    H. J. Chao and X. Guo

  2. "Methods and apparatus for shaping queued packets using a two-dimensional RAM-based search engine"
    patent no. 6,370,144, April 9, 2002
    H. J. Chao and Y. R. Jenq

  3. "Methods and apparatus for fairly scheduling queued packets using a RAM-based search engine"
    patent no. 6,389,031, May 14, 2002
    H. J. Chao and Y. R. Jenq

  4. "Methods and apparatus for a fast ring reservation arbitration"
    patent no. 6,449,283, Sep. 10, 2002
    H. J. Chao and A. Altinordu

  5. "Methods and apparatus for fairly arbitrating contention for an output port"
    patent no. 6,487,213, Nov. 26, 2002
    H. J. Chao

  6. "Methods and apparatus for arbitrating output port contention in a switch having virtual output queueing"
    patent no. 6,667,984, Dec. 23 2003
    H. J. Chao and J. S. Park

  7. "Scheduling the dispatch of cells in multistage switches"
    filed on May 8, 2001
    H. J. Chao and E. Oki

  8. "Scheduling the dispatch of cells in multistage switches using a hierarchical arbitration scheme for matching non-empty virtual output queues of a module with outgoing links of the module"
    filed on June 1, 2001
    H. J. Chao and E. Oki

  9. "Pipelined maximal-sized matching cell dispatch scheduling"
    filed on June 1, 2001
    E. Oki, R. Rojas-Cessa, and H. J. Chao

  10. "Scheduling the dispatch of cells in non-empty virtual output queues of multistage switches using a pipelined arbitration scheme"
    filed on July 23, 2001
    E. Oki, H. J. Chao, and R. Rojas-Cessa

  11. "Arbitration using dual round robin with exhaustive service of winning virtual output queue"
    file on Oct. 31, 2002
    H. J. Chao, Y. Li, and S. S. Panwar

  12. "Distributed architecture for statistical overload control against distributed denial of service attacks"
    filed on Nov. 26, 2003
    W. Lau, M. C. Chuah, Y. Kim, and H. J. Chao

  13. "Packet sequence maintenance with load balancing, and head-of-line blocking avoidance in a switch"
    filed in Jan. 2004
    H. J. Chao and J. S. Park

  14. "Switch module memory structure and per-destination queue flow control for use in a packet switch"
    filed in Feb. 2004
    H. J. Chao and J. S. Park

For the complete Patent List click here

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