PATENTS
P1. US
patent number 6052808
"Maintenance registers with boundary scan interface"
April 2000.
P2. Filed
for a patent entitled
"An apparatus for on-line testing using off-line test
resources" January 1998.
JOURNAL PAPERS
J1.
D. Sonecha,
B. Yang, R. Karri, D. A. Mcgrew "High-speed
architectures for binary-tree based stream ciphers:Leviathan
case study, " Journal of Microprocessors and Microsystems, to appear.
J2.
Kaijie
Wu, Ramesh Karri, " Fault Secure Datapath Synthesis using Hybrid Time and Hardware
Redundancy ", IEEE Transaction on Computer-Aided Design of Integrated
Circuits and Systems, Oct, 2004, Vol 23, No. 10, pp
1476-1484
J3.
Kaijie
Wu, Ramesh Karri, " Selectively Breaking Data
Dependences to Improve the Utilization of Idle Cycles in Algorithm Level
Re-Computing Data Paths ," IEEE Transactions on Reliability, Dec. 2003, Vol 52 , No. 4, pp 501 - 511
J4.
Ramesh
Karri, Piyush Mishra,
"Optimizing the energy consumed by secure wireless sessions - Wireless
Transport Layer Security case study", Journal of Mobile Networks and
Applications (MONET), Kluwer Academic Publishers,
April 2003, Vol. 8, No. 2, pp. 177-185.
J5.
Kaijie
Wu, Ramesh Karri, Piyush Mishra, "Concurrent Error Detection of Fault-Based
Side-Channel Cryptanalysis of 128-Bit RC6 Block Cipher,
" Special Issue on Defect and Fault Tolerance in VLSI Systems.
Microelectronics Journal, January 2003, Vol 34, No.
1, pp 31-39
J6.
Ramesh
Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim,
"Concurrent Error Detection Schemes for Fault Based Side-Channel
Cryptanalysis of Symmetric Block Ciphers, "IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems. December 2002, Vol 21. No. 12, pp 1509-1517
J7.
Ramesh
Karri, Kaijie Wu, " Algorithm Level Re-Computing
using Implementation Diversity: A Register Transfer Level Concurrent Error
Detection Technique, " IEEE Transactions on Very Large Scale Integration
(VLSI) Systems. December 2002, Vol 10. No. 6, pp 864
-875.
J8.
Kaijie
Wu, R. Karri, " Algorithm Level Recomputing Using
Allocation Diversity: A Register Transfer Level Approach To Time Redundancy
Based Concurrent Error Detection, " IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, September 2002, Vol
21. No. 9, pp 1077 -1087
J9.
Ramesh
Karri and B. Iyer, "Introspection: A Register
Transfer Level Technique for Concurrent Error Detection and Diagnosis in Data
Dominated Designs," ACM Transactions on Design Automation of Electronic
Systems, vol.7, no.1, Jan 2002.
J10.
M. Veeraraghavan,
Ramesh Karri, T. Moors, M. Karol and R. Grobler, "Architectures and protocols that enable new
applications on optical networks," IEEE Communications Magazine, vol. 39,
no. 3, Mar 2001.
J11.
Ramesh
Karri, Kyosun Kim and M. Potkonjak,
"Computer Aided Design of Fault Tolerant Application Specific Programmable
Processors," IEEE Transactions on Computers, vol
49, no 11, pp. 1272-1284, Nov 2000.
J12.
I Hong, M. Potkonjak and Ramesh Karri,
"Power optimization using Divide-and-Conquer for Minimization of the
Number of Operations," ACM Transactions on Design Automation of Electronic
Systems, vol 6, no. 4, Oct 1999.
J13.
N. Mukherjee,
T. Chakraborty and Ramesh
Karri, "Built-In Self Test: A Complete Test Solution for Communication
Systems," IEEE Communications Magazine, vol. 37, no. 6, pp. 72-78, Jun
1999.
J14.
N. Mukherjee
and Ramesh Karri, "An Integrated approach to
On-Line/Off-Line BIST," Journal of Electronic Testing and Testability
Analysis, pp. 189-200, Dec 1998.
J15.
A. Dasgupta
and Ramesh Karri, "High-Reliability Low-Energy Microarchitecture Synthesis," IEEE Transactions on
CAD, vol. 17, no. 12, pp. 1273-1280, Dec 1998.
J16.
Ramesh
Karri, Karen Hogstedt and A. Orailoglu,
"Computer Aided Design of Fault Tolerant VLSI Systems," IEEE Design
& Test of Computers, vol. 13, no.3, pp. 88-96, Fall 1996.
J17.
Ramesh
Karri and A. Orailoglu, "Time constrained
scheduling during high level synthesis of Fault-Secure VLSI Digital Signal
Processors," IEEE Transactions on Reliability, vol. 45, no.3, pp. 404-412,
Sep 1996.
J18.
A. Orailoglu
and Ramesh Karri, "Automatic Synthesis of
Self-Recovering VLSI Systems," IEEE Transactions on Computers, vol.45,
no.2, pp. 131-142, Feb 1996.
J19.
A. Dasgupta
and Ramesh Karri, "Optimal Algorithms for
Synthesis of Reliable Application Specific Heterogeneous Multiprocessors,"
IEEE Transactions on Reliability, vol. 44, no. 4, pp. 603-613, Dec 1995.
J20.
A. Orailoglu
and Ramesh Karri, "Coactive Scheduling and
Checkpoint Determination during High Level Synthesis of Self-Recovering Microarchitectures," IEEE Transactions on VLSI
Systems, vol 2, no. 3, pp. 304-311, Sep 1994.
J21.
A. Orailoglu
and Ramesh Karri, "Defect Tolerant Layout
Synthesis," International Journal of Electronics, pp. 1121-1133, Jun 1994.
J22.
A. Orailoglu
and Ramesh Karri, "Synthesis of Fault-Tolerant
and Real Time Micro architectures," Journal of Systems and Software, pp.
73-84, May 1994.
J23.
Ramesh
Karri and Alex Orailoglu, "Standard seven
segment display for Burmese Numerals," IEEE Transactions on Consumer
Electronics, vol. 36, no. 4, pp. 959-961, Nov 1990.
SHORT
JOURNAL COMMUNICATIONS
J24.
Ramesh
Karri, "Guest editors introduction to special section on High Level Design
Validation and Test," IEEE Transactions on CAD, vol. 20, no. 2, Mar 2001.
J25.
Ramesh
Karri and M. Nicolaidis, "Online VLSI Testing -
Guest Editors introduction," IEEE Design and Test of Computers, vol 15, no. 4, pp 12-16, Oct-Dec 1998.
RIGOROUSLY
REFEREED CONFERENCE PAPERS
C1.
Wenjing
Rao, Alex Orailoglu, Ramesh Karri, "Fault Tolerant Arithmetic with
Applications in Nanotechnology based System" International Test Conference
2004, Charlotte.
C2.
Kaijie
Wu, Ramesh Karri, Grigori Kuznetsov, Michael Goessel, "Parity Based Concurrent
Error Detection for the Advanced Encryption Standard", International Test
Conference 2004, Charlotte.
C3.
Bo Yang, Kaijie Wu, Ramesh Karri, "Scan-based
Side-Channel Attack on Dedicated Hardware Implementations of Data Encryption
Standard" International Test Conference 2004, Charlotte.
C4.
B. Yang, R. Karri, D. A.
Mcgrew, "Divide-and-concatenate: an architecture
level optimization technique for universal hash functions", IEEE/ACM
Design Automation Conference (DAC),June, 2004, San Diego.
C5.
Kaijie
Wu, Ramesh Karri, "Register Transfer Level
Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis", International Test Conference
2003, Charlotte.
C6.
Kaijie
Wu, Ramesh Karri, "Exploiting idle cycles for
algorithm level re-computing," Design Automation and Test in Europe
(DATE), 2002, Paris.
C7.
Kaijie
Wu, Ramesh Karri, "Algorithm Level Re-Computing
- A Register Transfer Level Concurrent Error Detection Technique,"
International Conference on Computer Aided Design 2001, San Jose.
C8.
Kaijie
Wu, Ramesh Karri, "Algorithm Level Re-Computing
with Allocation Diversity: A Register Transfer Level Time Redundancy Based
Concurrent Error Detection Technique," International Test Conference 2001,
Baltimore.
C9.
Ramesh
Karri, K. Wu, Y. Kim and P. Mishra, "Concurrent
error detection schemes for side-channel fault analysis of 128-bit symmetric block
ciphers" Proceedings of IEEE/ACM Design Automation Conference, Las Vegas,
NV, Jun 2001.
C10.
K. Wu and Ramesh Karri "Algorithmic Level Recomputing
with Shifted Operands- A High Level Synthesis Approach to Concurrent Error
Detection," Proceedings of IEEE International Test Conference,
C11.
Ramesh
Karri and
C12.
Kyosun
Kim, Ramesh Karri and M. Potkonjak,
"Micro-Preemption Synthesis: An Enabling Mechanism for Multi-Task VLSI
Systems," Proceedings of IEEE International Conference on CAD,
C13.
Inki
Hong, M. Potkonjak and Ramesh
Karri, "Compilation and architecture techniques for power optimization of
real-time DSP applications on programmable platforms," Proceedings of IEEE
International Conference on CAD,
C14.
C. Stroud, M. Ding, S. Seshadri, I. Kim, S. Roy S. Wu and R. Karri, "A Parametrized VHDL Library for On-Line Testing,"
Proceedings of IEEE International Test Conference, Washington DC, Nov 1997.
C15.
Kyosun
Kim, Ramesh Karri and M. Potkonjak,
"Synthesis of Application Specific Programmable Processors,"
Proceedings of IEEE/ACM Design Automation Conference, Sanfrancisco,
CA, Jun 1997.
C16.
M. Potkonjak,
Kyosun Kim and Ramesh
Karri, "Synthesis and Selection of DCT Algorithms using Behavioral
Synthesis-based Algorithm Space Exploration," Proceedings of IEEE/ACM
Design Automation Conference, Sanfrancisco, CA, Jun
1997.
C17.
Kyosun
Kim, Ramesh Karri and M. Potkonjak,
"Heterogeneous Built-In Resiliency of Application Specific Programmable
Processors," Proceedings of IEEE International Conference on CAD,
C18.
A Dasgupta
and Ramesh Karri, "Hot-Electron Reliability Enhancement
via Gate input Reordering," Proceedings of IEEE/ACM Design Automation
Conference, Las Vegas, NV, Jun 1996.
C19.
A Dasgupta
and Ramesh Karri, "Electromigration
Reliability Enhancement via Bus Activity Distribution," Proceedings of
IEEE/ACM Design Automation Conference,
C20.
B Iyer
and Ramesh Karri, "Introspection: A zero
overhead binding technique during self-diagnosing microarchitecture
synthesis," Proceedings of IEEE/ACM Design Automation Conference,
C21.
B Iyer,
Ramesh Karri and I Koren,
"Phantom Redundancy: A High-Level Synthesis Technique for
Manufacturability," Proceedings of IEEE International Conference on CAD,
C22.
Ramesh
Karri and A Orailoglu,
"Area-Efficient Fault-Detection during Self-Recovering Microarchitectures
Synthesis," Proceedings of IEEE/ACM Design Automation Conference,
C23.
Ramesh
Karri and A Orailoglu,
"Synthesis of Optimal Self-Recovering Microarchitectures,"
Proceedings of IEEE International Symposium on Fault-Tolerant Computing,
C24.
Ramesh
Karri and A Orailoglu,
"High-Level Synthesis of Fault-Secure Microarchitectures,"
Proceedings of IEEE/ACM Design Automation Conference,
C25.
Ramesh
Karri and A Orailoglu,
"Scheduling with Rollback Constraints in High-Level Synthesis of
Self-Recovering ASICs," Proceedings of IEEE
International Symposium on Fault-Tolerant Computing,
C26.
Ramesh
Karri and A Orailoglu,
"Transformation-Based Synthesis of Fault-Tolerant ASICs,"
Proceedings of IEEE/ACM Design Automation Conference,
C27.
Ramesh
Karri, "Security imbedded authentication protocol," Proceedings of
the IEEE INFOCOM,
REFEREED
CONFERENCE PAPERS
C28.
Wenjing
Rao, Alex Orailoglu, Ramesh Karri, "Fault Tolerant Nanoelectronic
Processor Architectures," Asia and South Pacific Design Automation
Conference,
C29.
Tongquan
Wei, Kaijie Wu, Ramesh Karri, Alex Orailoglu,
"Fault Tolerant Quantum Cellular Array (QCA) Design using Triple Modular
Redundancy with Shifted Operands," Asia and South Pacific Design
Automation Conference, Shanghai, China, Jan 2005.
C30.
Nikhil Joshi, Kaijie Wu, Ramesh Karri,
"Concurrent Error Detection Schemes for Involution Ciphers," Workshop
on Cryptographic Hardware and Embedded Systems, 2004,
C31.
Ramesh
Karri, Piyush Mishra,
"Investigation into the energy consumption characteristics of secure
wireless session establishment and management," IEEE Global Communications
Conference,
C32.
Ramesh
Karri, Piyush Mishra,
"Analysis of energy consumed by secure session negotiation protocols in
wireless networks," International Workshop on Power and Timing Modeling,
Optimization and Simulation, Torino, Italy, Sep 2003,
Springer-Verlag Lecture Notes in Computer Science,
Integrated Circuit and System Design.
C33.
Ramesh
Karri, Piyush Mishra,
"Design of energy efficient secure wireless networks using network
simulators," Proceedings, IEEE International Conference on Communication,
C34.
Ramesh
Karri, Piyush Mishra,
"Minimization of energy consumption of secure wireless session with QoS constraints," Proceedings, IEEE International
Conference on Communication,
C35.
Khary
Alexander, Ramesh Karri, Igor Minkin,
Kaijie Wu, Piyush Mishra, Xuan Li , " Towards
10-100 Gbps Cryptographic Architectures, "
International Symposium On Computer and Information Sciences, 2002, Orlando.
C36.
Ramesh
Karri, Kaijie Wu, Piyush Mishra, Yongkook Kim, "
Fault-based side-channel cryptanalysis tolerant Rijndael
symmetric block cipher architecture," IEEE International Symposium on
Defect and Fault Tolerance in VLSI Systems 2001, San Francisco.
C37.
Kaijie
Wu, Ramesh Karri, "Idle cycles based concurrent
error detection of RC6 encryption," IEEE International Symposium on Defect
and Fault Tolerance in VLSI Systems 2001, San Francisco.
C38.
J. Karrfalt,
Ramesh Karri, Mark Brown, "Automatic
Reconfiguration Tool," Proceedings of Government Microelectronics
Application Conference, San Antonio, TX, Mar 2001.
C39.
R. Karri, K. Wu, Y. Kim
and P. Mishra, "Concurrent error detection
architectures for symmetric block ciphers," Proceedings of NASA workshop
on Military Applications of Programmable Designs and Technologies, Greenbelt,
MD, Sep 2000.
C40.
K. Wu and Ramesh Karri "Algorithmic Level Recomputing
with Shifted Operands- A High Level Synthesis Approach to Concurrent Error
Detection," Proceedings of NASA workshop on Military Applications of
Programmable Designs and Technologies, Greenbelt, MD, Sep 2000.
C41.
R. Karri, K. Kim and M. Potkonjak, "Design Trade-offs during fault-tolerant
data path synthesis", Proceedings of IEEE International Workshop on High
Level Design Validation and Test, San Diego, CA, Nov 1999.
C42.
R. Karri N. Mukherjee and T. Chakrabarti,
"Register Transfer Level approaches to on-line testing", Proceedings
of IEEE International Workshop on On-Line Testing, Rhodes, Greece, Jul 1999.
C43.
K. Kim, R. Karri and M. Potkonjak, " Synthesis of Fault-Tolerant Application
Specific Programmable Processors'', Proceedings of IEEE International Workshop
on High Level Design Validation and Test,
C44.
Ramesh
Karri and
C45.
Ramesh
Karri, C. Stroud, and M. Ding, "Issues in Developing a Parametrized
VHDL Library for On-Line Testing," Proceedings of Lucent Conference on
Electronic Testing,
C46.
Inki
Hong, M. Potkonjak and Ramesh
Karri, "Heterogeneous BISR-Approach Using System Level Synthesis
Flexibility," Proceedings of IEEE Asia and South Pacific Design Automation
Conference, Feb 1998.
C47.
Kyosun
Kim, Ramesh Karri and M. Potkonjak,
"Configurable Spare Processors: A new approach to system level
fault-tolerance," Proceedings of IEEE International Symposium on Defect
and Fault Tolerance in VLSI,
C48.
Kyosun
Kim, Ramesh Karri and M. Potkonjak,
"Maximizing the Fault-Tolerance of Application Specific Signal
Processors," Proceedings of IEEE workshop on VLSI Signal Processing,
C49.
A Dasgupta
and Ramesh Karri, "RELSYN: A tool for synthesis
of Reliable Application Specific Multiprocessor," Proceedings of IEEE
International Symposium on Circuits and Systems, May 1996.
C50.
A Dasgupta
and Ramesh Karri, "Switch-Level Hot-Carrier
Reliability Enhancement of VLSI Circuits," Proceedings of IEEE
International Workshop on Defect and Fault Tolerance in VLSI Systems,
C51.
A Dasgupta
and Ramesh Karri, "Synthesis of Reliable
Application Specific Heterogeneous Multiprocessor Systems," Proceedings of
IEEE International Symposium on Circuits and Systems,
C52.
A Dasgupta
and Ramesh Karri, "Simultaneous Scheduling and Binding for Power Minimization During Microarchitecture Synthesis," Proceedings of IEEE
International Symposium on Low Power Design, Dana point, CA, Apr 1995.
C53.
C54.
Ramesh
Karri, A Orailoglu and K Hogstedt,
"Rapid Prototyping of Fault Tolerant VLSI Systems," Proceedings of
IEEE High Level Synthesis Workshop, Dana point, CA, May 1994.
C55.
A
Orailoglu and Ramesh Karri,
"Simulated Annealing Based Yield Enhancement of Layouts," Proceedings
of IEEE
C56.
Ramesh
Karri and A Orailoglu, "A Framework For
Synthesizing Fault-Tolerant Microarchitectures,"
Proceedings of IEEE Custom Integrated Circuits Conference, San Diego, CA, May
1993.
C57.
A
Orailoglu and Ramesh Karri,
"A Design Methodology for the High-Level Synthesis of Fault-Tolerant ASICs," Proceedings of IEEE Workshop on VLSI Signal
Processing,
C58.
Ramesh
Karri and A Orailoglu,
"Transformation-Based Register Optimization in High-Level Synthesis,"
Proceedings of IEEE Asilomar Conference on Circuits
and Systems,