EL 737   HIGH PERFORMANCE SWITCHED AND ROUTERS
(Spring'07: Thursday 3:35-5:50 pm)

 

Come to learn how to design high performance switches and routers for today’s ever growing Internet traffic

As more and more voice, audio, video, TV, and gaming traffic is carried over IP, the Internet traffic continues to grow rapidly, posing the need of deploying high performance large-capacity switches and routers in the Internet. This course addresses the basics, the theory, architectures, and technologies to implement such high-end switches and routers. The course starts with an introduction to today’s and tomorrow’s networks, the router architectures and their building blocks, examples of commercial high-end routers, and the challenging issues of designing high-performance high-speed routers.  Topics to be included are listed in following table.

Prerequisites: EL 536, or advisor approval

                                                                  
 

Week

Contents

01

Introduction to routers

02

IP route lookup I

03

IP route lookup II

04

Packet classification I

05

Packet classification II

06

Quality of service control

07

Shared memory switches

08

Input buffered switches I

09

Input buffered switches II

10

Crosspoint-buffered switches

11

Load balanced switches

12

Multi-stage switches


  • Textbook
    • High Performance Switches and Routers, a 3rd book from Prof.H. Jonathan Chao, to be published by John Wiley. Manuscript is available for the class.
  • Instructor: Prof.H. Jonathan Chao, Office: LC 262, TEL: 718-260-3302
  • E-mail:  chao@poly.edu,URL: http://eeweb.poly.edu/~chao
  • Grading:  Homework and Quizzes: 30%, Midterm: 30%, Term project: 40%

    • Prof. Chao is Department Head and Professor of Electrical and Computer Engineering at Polytechnic University, New York, NY, where he joined in January 1992. He has been doing research in the areas of network security, terabit switches/routers, quality of service control, and optical networking and switching. He holds 26 patents and has published over 150 journal and conference papers in the above areas. During 2000–2001, he was Co-Founder and CTO of Coree Networks, NJ, where he led a team to implement a multi-terabit router with carrier-class reliability. From 1985 to 1992, he was a Member of Technical Staff at Telcordia, where he conducted research in high-speed network transmission and switching systems and their ASIC implementations. He is a Fellow of the IEEE for his contributions to the architecture and application of VLSI circuits in high-speed packet networks.