PATENTS


  1. "Framer circuit for use in DTDM (Dynamic Time-Division Multiplexing) network"
    patent no. 4,819,226, Apr. 1989
    M. Beckner, H. J. Chao, and T. Robe

  2. "Time division multiplexer for DTDM bit streams"
    patent no. 4,833,673, May 1989
    H. J. Chao and S. Lee

  3. "DTDM multiplexer with cross-point switch"
    patent no. 4,855,999, Aug. 1989
    H. J. Chao

  4. "Method and apparatus for multiplexing circuit and packet traffic"
    patent no. 4,893,306, Jan. 1990
    H. J. Chao, S. Lee, and L. Wu

  5. "Service clock recovery circuit"
    patent no. 5,007,070, Apr. 1991
    H. J. Chao and C. Johnston

  6. "Optical customer premises network"
    patent no. 5,050,164, Sep. 1991
    H. J. Chao, G. Shtirmer, and L. S. Smoot

  7. "Customer premises network node access protocol"
    patent no. 5,079,763, Jan. 1992
    H. J. Chao, G. Shtirmer, and L. S. Smoot

  8. "Grouping network based non-buffer statistical multiplexer"
    patent no. 5,124,978, June 1992
    H. J. Chao

  9. "Crosspoint matrix switching element for a packet switch"
    patent no. 5,179,552, Jan. 1993
    H. J. Chao

  10. "Distributed modular packet switch employing recursive partitioning"
    patent no. 5,179,064, Mar. 1993 (patent has been licensed to AT&T)
    H. J. Chao

  11. "Service clock recovery for variable bit rate services"
    patent no. 5,204,882, Apr. 1993 (patent has been licensed to AT&T)
    H. J. Chao and C. Johnston

  12. "Method and system for managing queued cells"
    patent no. 5,278,828, Jan. 1994 (patent has been licensed to AT&T)
    H. J. Chao

  13. "B-ISDN Sequencer chip device"
    patent no. 5,313,579, May 1994
    H. J. Chao

  14. "Method and system for controlling user traffic to a fast packet switching system"
    patent no. 5,381,407, Jan. 1995
    H. J. Chao

  15. "A scalable multicast ATM switch"
    patent no. 5,724,351, March 1998
    H. J. Chao and B. S. Choe

  16. "ASIC chip for implementing a scalable multicast ATM switch"
    patent no. 5,790,539, Aug. 1998
    H. J. Chao and N. Uzun

  17. "Methods and apparatus for handling time stamp aging"
    patent no. 6,081,507, June 2000
    H. J. Chao and X. Guo

  18. "Methods and apparatus for shaping queued packets using a two-dimensional RAM-based search engine"
    patent no. 6,370,144, April 9, 2002
    H. J. Chao and Y. R. Jenq

  19. "Methods and apparatus for fairly scheduling queued packets using a RAM-based search engine"
    patent no. 6,389,031, May 14, 2002
    H. J. Chao and Y. R. Jenq

  20. "Methods and apparatus for a fast ring reservation arbitration"
    patent no. 6,449,283, Sep. 10, 2002
    H. J. Chao and A. Altinordu

  21. "Methods and apparatus for fairly arbitrating contention for an output port"
    patent no. 6,487,213, Nov. 26, 2002
    H. J. Chao

  22. "Methods and apparatus for arbitrating output port contention in a switch having virtual output queueing"
    patent no. 6,667,984, Dec. 23 2003
    H. J. Chao and J. S. Park

  23. "Scheduling the dispatch of cells in multistage switches"
    filed on May 8, 2001
    H. J. Chao and E. Oki

  24. "Scheduling the dispatch of cells in multistage switches using a hierarchical arbitration scheme for matching non-empty virtual output queues of a module with outgoing links of the module"
    filed on June 1, 2001
    H. J. Chao and E. Oki

  25. "Pipelined maximal-sized matching cell dispatch scheduling"
    filed on June 1, 2001
    E. Oki, R. Rojas-Cessa, and H. J. Chao

  26. "Scheduling the dispatch of cells in non-empty virtual output queues of multistage switches using a pipelined arbitration scheme"
    filed on July 23, 2001, patent no. 6,940,851, Sep. 6, 2005.
    E. Oki, H. J. Chao, and R. Rojas-Cessa

  27. "Scheduling the dispatch of cells in non-empty virtual output queues of multistage switches using a pipelined hierarchical arbitration scheme"
    filed on July 23, 2001 ,patent no. 7,046,661 , May 16, 2006
    E. Oki, H. J. Chao, and R. Rojas-Cessa

  28. "Arbitration using dual round robin with exhaustive service of winning virtual output queue"
    file on Oct. 31, 2002
    H. J. Chao, Y. Li, and S. S. Panwar

  29. "Distributed architecture for statistical overload control against distributed denial of service attacks"
    filed on Nov. 26, 2003
    W. Lau, M. C. Chuah, Y. Kim, and H. J. Chao

  30. "Packet sequence maintenance with load balancing, and head-of-line blocking avoidance in a switch"
    filed in Feb. 11, 2004
    H. J. Chao and J. S. Park

  31. "Switch module memory structure and per-destination queue flow control for use in a packet switch"
    filed in Feb. 11, 2004
    H. J. Chao and J. S. Park

  32. "Packet reassembly and deadlock avoidance for use in a packet switch"
    file on June 18, 2004
    H. J. Chao and J. S. Park

  33. "Packet-level multicasting"
    filed on June 18, 2004
    H. J. Chao and J. S. Park

  34. "Maintaining packet sequence using cell flow control"
    filed on Dec. 3, 2004
    H. J. Chao and J. S. Park

  35. "Providing a high-speed defense against distributed denial of service (DDoS) attacks"
    filed on June 6, 2006
    H. J. Chao and H. Sun

  36. "Determining rerouting information for single-link failure recovery in an Internet protocol network"
    filed on April 10, 2007.
    H. J. Chao and K. Xi

  37. "Determining rerouting information for single-node failure recovery in an Internet protocol network"
    filed on April 10, 2007.
    H. J. Chao and K. Xi

  38. "Generating a hierarchical data structure associated with a plurality of known arbitrary-length bit strings used for detecting whether an arbitrary-length bit string input matches one of a plurality of known arbitrary-length bit strings"
    filed on October 26, 2007.
    S. Artan and H. J. Chao

  39. "Detecting whether an arbitrary-length bit string input matches one of a plurality of known arbitrary-length bit strings using a hierarchical data structure"
    filed on October 26, 2007
    S. Artan and H. J. Chao