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PACKET SWITCHES


 • Input Buffered Switches
 • Clos-Network Buffered Switches
 • Clos-Network Bufferless Switches
 • Crosspoint-Buffered Switches
 • Optical Packet Switches
 • Generalized Knockout Switches
 • Fault-Tolerant Switches
 • Wireless ATM Switches
 • Load Balanced Switches


Input Buffered Switches
  1. "Packet Delay-Aware Scheduling in Input Queued Switches"
    Y. Li, S. Panwar, H. J. Chao, and J. Lee
    IEEE GLOBECOM 2006, St. Francisco, CA, Nov. 27-30, 2006.

  2. "Byte-Focal: a practical load-balanced switch"
    Y. Shen, S. Jiang, S. S. Panwar, and H. J. Chao
    IEEE Workshop on High Performance Switching and Routing, Hong Kong, May 2005.

  3. "Exhaustive Service Matching Algorithms for Input Queued Switches"
    Y. Li, S. Panwar, H. J. Chao
    IEEE Workshop on High Performance Switching and Routing, Phoenix, AZ, April 2004

  4. "Frame-based Matching Algorithms for Optical Switches"
    Y. Li, S. Panwar, H. J. Chao
    IEEE Workshop on High Performance Switching and Routing, Torino, Italy, June 2003

  5. "Performance of exhaustive matching algorithms for input-queued switches"
    Y. Kim and H. J. Chao
    IEEE ICC 2003, Anchorage, Alaska, May 2003

  6. "Performance analysis of a dual round robin matching switch with exhaustive service"
    Y. Li, S. Panwar, and H. J. Chao
    IEEE Globecom, Taiwan, Nov. 2002

  7. "A Pipeline-Based Maximal-Sized Matching Scheme for High-Speed Input-Buffered Switches"
    E. Oki, R. Rojas-Cessa, and H. J. Chao
    in IEICE Trans. Commun, vol. E85-B, no. 7, pp. 1302-1311, July 2002

  8. "The dual round robin matching switch with exhaustive service"
    Y. Li, S. Panwar, and H. J. Chao
    IEEE Workshop on High Performance Switching and Routing, Kobe, May 2002

  9. "A Pipeline-Based Approach for a Maximal-Sized Matching Scheduling in Input-Buffered Switches"
    E. Oki, R. Rojas-Cessa, and H. J. Chao
    IEEE Communication Letters, vol. 5, no. 6, pp. 263-265, June 2001.

  10. "A fast arbitration scheme for terabit packet switches"
    H. J. Chao, C. H. Lam and X. Guo
    IEEE Global Telecommunications Conference (GLOBECOM), vol. 2, pp. 1236-1243, 1999

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Clos-Network Buffered Switches
  1. "Flow control in a multi-plane multi-stage buffered packet switch"
    H. J. Chao and J. Park
    2007 IEEE Workshop on High Performance Switching and Routing, Brooklyn, NY ,May 2007

  2. "TrueWay: A highly scalable multi-plane multi-stage buffered switch"
    H. J. Chao, J. S. Park, S. Artan, S. Jiang, and G. Zhang
    IEEE Workshop on High Performance Switching and Routing, Hong Kong, May 2005.

  3. "Maximum Weight Matching Dispatching Scheme in Buffered Clos-network Packet Switches"
    R. Rojas-Cessa, E. Oki, and H. J. Chao
    IEEE ICC 2004, Paris, France, June 2004

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Clos-Network Bufferless Switches
  1. "Matching Algorithms for Three-Stage Bufferless Clos-Network Switches"
    H. J. Chao, Z. Jing, and S. Y. Liew
    invited paper, in IEEE Communication Magazine, pp. 46-53, Oct. 2003

  2. "A Dual-Level Matching Algorithm for 3-Stage Clos-Network Packet Switches"
    H. J. Chao, S. Y. Liew, and Z. Jing
    HOT Interconnects, Stanford Univ, CA, Aug. 2003

  3. "Concurrent Round-Robin-Based Dispatching Schemes for Clos-Network Switches"
    E. Oki, Z. Jing, R. Rojas-Cessa, and H. J. Chao
    in IEEE/ACM Trans. on Networking, vol. 10, no. 6, pp. 830-844, Dec. 2002

  4. "PCRRD: A pipeline-based concurrent round-robin dispatching scheme for Clos-network switches"
    E. Oki, R. Rojas-Cessa, and H. J. Chao
    IEEE ICC 2002, New York, April 2002

  5. "Concurrent Round-Robin Dispatching Scheme in a Clos-Network Switch"
    E. Oki, Z. Jing, R. Rojas-Cessa and H. J. Chao
    in IEEE ICC, Helsinki, June 2001.

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Crosspoint-Buffered Switches
  1. "A Low Complexity Scheduling Algorithm for a Crosspoint Buffered Switch with 100% Throughput"
    Y. Shen, S. Panwar, and H. J. Chao
    2007 IEEE Workshop on High Performance Switching and Routing, May 2008, Shanghai, China, May 2008.

  2. "On the combined input-crosspoint buffered switch and round-robin arbitration"
    R. Rojas-Cessa, E. Oki, and H. J. Chao
    to appear in IEEE Trans. on Communications. pp. 141-155, April-June, 2006.

  3. "CIXOB-k: Combined Input-Crosspoint-Output Buffered Packet Switch"
    Rojas-Cessa, E. Oki, and H. J. Chao
    in IEEE Globecom Conference, San Antonio, Texas, Nov. 2001.

  4. "CIXB-1: Combined Input-Once-Cell-Crosspoint Buffered Switch"
    Rojas-Cessa, E. Oki, Z. Jing, and H. J. Chao
    IEEE Workshop on High Performance Switching and Routing, Dallas, TX, July 2001.

  5. "Performance analysis of a large-scale multicast output buffered ATM switch"
    B. S. Choe and H. J. Chao
    in IEEE Proc. INFOCOM'94, Torando, Canada, June 1994.

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Optical Packet Switches
  1. "Design of Cell Edge Routers in the Optical Cell Switch (OCS) Network"
    S. Jiang and H. J. Chao
    IEEE GLOBECOM 2005, Nov. 28-Dec 2, 2005, St Louis, MO.

  2. "Scheduling algorithms for shared fiber-delay-line optical packet switches, Part I: The single-stage case"
    S. Y. Liew, G. Hu, and H. J. Chao
    IEEE Journal of Lightwave Technology., April 2005.

  3. "Scheduling algorithms for shared fiber-delay-line optical packet switches, Part II: The 3-stage Clos-Network case"
    S. Y. Liew, G. Hu, H. J. Chao
    IEEE Journal of Lightwave Technology., April 2005.

  4. "An optical packet switch based on WDM technologies, to appear in IEEE Journal of Lightwave Technology. "
    X. Yu, L. Lin, X. Zhao, J. P. Zhang, Y. Gu, F. S. Choa, G. Zhang, L. Li, H. Xiang, H. Hadimioglu,H. J. Chao
    IEEE Journal of Lightwave Technology., March 2005.

  5. "Scheduling Algorithms for Shared Fiber-Delay-Line Optical Packet Switches, Part I: The Single-Stage Case"
    S. Y. Liew, G. Hu, H. J. Chao
    IEEE GLOBECOM 2004, Dallas, TX, Nov. 2004

  6. "Scheduling Algorithms for Shared-Fiber-Delay-Line Optical Cell Switches"
    S. Y. Liew and H. J. Chao
    Optical Fiber Communications (OFC), Los Angeles, CA, Feb. 2004

  7. "A New Optical Cell Switching Paradigm"
    H. J. Chao and S. Y. Liew
    International Workshop on Optical Burst Switching, Dallas, TX, Oct. 2003

  8. "PetaStar: A petabit photonic packet switch"
    H. J. Chao, Z. Jing, and K. Deng
    in IEEE Journal on Selected Areas in Communications (JSAC), Special Issue on High-Performance Optical/Electronic Switches/Routers for High-Speed Internet, vol. 21, no. 7, pp. 1096-1112, Sep. 2003

  9. "Guest editorial high-performance optical switches/routers for high-speed internet"
    M. Hamdi, H. J. Chao, D. J. Blumental, E Leornardi, Chumming Qiao, K. Y. Yun and R. Ramaswami
    IEEE Journal on Selected Areas in Communications, vol. 21, no. 7, pp. 1013-1017, Sept 2003

  10. "On Slotted WDM Switching in Bufferless All-Optical Networks"
    S. Y. Liew and H. J. Chao
    HOT Interconnects, Stanford Univ, CA, Aug. 2003

  11. "Packet scheduling scheme for a 3-stage Clos-network photonic switch"
    H. J. Chao, K. L. Deng, and Z. Jing
    IEEE ICC 2003, Anchorage, Alaska, May 2003

  12. "Petabit Photonic Packet Switch (P3S)"
    H. J. Chao, K-L. Deng, and Z. Jing
    IEEE INFOCOM, San Francisco, April 1-3, 2003

  13.   "Frame-based exhaustive matching (FEM) scheme for photonic packet switch"
    Kung-Li Deng, H. J. Chao and Zhigang Jing
    The 15th Annual Meeting of IEEE Lasers and Electro-Optics Society, vol. 1, pp. 349-350, Nov 2002

  14. "An Optical Interconnection Network for Terabit IP Routers"
    H. J. Chao and T. S. Wang
    IEEE Journal of Lightwave Technology, vol. 18, no. 12, pp. 2095-2112, Dec. 2000.

  15. "An FPGA Controlled WDM Buffer Memory"
    L. Wu, H. J. Chao, X. J. Zhao, Y. Zhao, Y. Chai, J. P. Zhang and F. S. Choa
    Conference on Lasers and Electro-Optics, pp. 340-341, May. 2000.

  16. "A photonic front-end processor in a WDM ATM multicast switch"
    H. J. Chao, et. al
    IEEE Journal of Lightwave Technology, Vol. 18, No. 3, pp. 273-285, March 2000.

  17. "Transparent all-optical packet routing - one network for all traffic"
    F. S. Choa and H. J. Chao
    in European Conference on Networks and Optical Communications, Delft, Netherlands, June 22-24, 1999.

  18. "All-optical packet routing - architecture and implementation"
    F. S. Choa and H. J. Chao
    Journal of Photonic Network Communications, Vol. 1, No. 4, pp. 303-311, 1999.

  19. "A Terabit IP Switch Router Using Optoelectronic Technology"
    H. J. Chao, X. Guo, C. H. Lam, and T. S. Wang
    (invited), The Journal of High speed Networks, Vol. 8, No. 1, April 1999.

  20. "A 2.5 Gbit/s optical ATM cell synchronizer"
    H. J. Chao, L. Wu, Z. Zhang, S. H. Yang, L. M. Wang, Y. Chai, J. Y. Fan and F. S. Choa
    The International Conference on Integrated Optics and Optical Fiber Communication
    Technical Optical Fiber Communication Conference, vol. 2, pp. 347-349, Feb. 1999.

  21.   "A Photonic ATM Front-End Processor"
    H. J. Chao, Z. Zhang, L. Wu, S. Yang, F. S. Choa and L. Wang
    IEEE Lasers and Electro-Optics Society Annual Meeting, vol. 1, pp. 287-288, Dec. 1998

  22.   "A Photonic ATM Front-End Processor"
    J. Y. Fan, L. M. Wang, Y. Chai, F. S. Choa, H. J. Chao, Z. Zhang, L. Wu and S Yang
    24th European Conference on Optical Communications, vol. 1, pp. 245-246, Sep. 1998

  23.   "Centralized contention resolution schemes for a large-capacity optical ATM switch"
    H. J. Chao and Jin-Soo Park
    IEEE ATM workshop Proceedings, pp. 11-16, May 1998

  24.   "Terabit/s ATM switch with optical interconnection network"
    H. J. Chao, Jin-Soo Park and Ti-Shiang Wang
    IEEE Lasers and Electro-Optics Society Annual Meeting, vol. 1, pp. 11-16, Nov. 1997

  25. "On the optically transparent WDM ATM Multicast (3M) switches"
    F. S. Choa and H. J. Chao
    in Fiber and Integrated Optics, Vol. 15, pp. 109-123, 1996.

  26. "Transport of gigabit/sec data packets over SONET/ATM networks"
    H. J. Chao, D. T. Kong, N. K. Cheung, M. Arnould and H. T. Kung
    IEEE Slobal Telecommunications Conference (GLOBECOM), Vol. 2, pp. 968-975, Dec. 1991.

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Generalized Knockout Switches
  1. "Design and analysis of enhanced Abacus switch"
    J. S. Park and H. J. Chao
    Computer Communications, vol. 25, no. 6, pp. 577 589, April 2002

  2. "Design and implementation of Abacus switch: A scalable multicast ATM switch"
    H. J. Chao, B. S. Choe, J. S. Park, and N. Uzun
    IEEE J. Select. Areas Commun., Vol. 15, No. 5, pp.830-843, June 1997.

  3. "Design and analysis of a large-scale multicast output buffered ATM switch"
    H. J. Chao and B. S. Choe
    IEEE/ACM Trans. on Networking, vol. 3, no. 2, pp. 112-138, Apr. 1995.

  4. "A recursive modular Terabit/sec ATM switch"
    H. J. Chao
    IEEE J. Select. Areas Commun., vol. 9, no. 8, pp. 1161-1172, Oct. 1991.

  5. "A distributed modular tera-bit/sec ATM switch"
    H. J. Chao
    IEEE Global Telecomunications Conference (GLOBECOM), vol. 3, pp. 1594-1601, Dec 1990

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Fault-Tolerant Switches
  1. "Concurrent fault detection for a multiple-plane packet switch"
    R. Rojas-Cessa, E. Oki, and H. J. Chao
    in IEEE/ACM Trans. on Networking, vol. 11, no. 4, pp. 616-627, Aug. 2003

  2. "Fast Fault Detection for a Multiple-plane Packet Switch"
    Rojas-Cessa, E. Oki, and H. J. Chao
    in IEEE Globecom Conference, San Antonio, Texas, Nov. 2001.

  3. "Fault-tolerance of a large-scale multicast output buffered ATM switch"
    B. S. Choe and H. J. Chao
    in IEEE Proc. INFOCOM'94, Torando, Canada, June 1994.

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Wireless ATM Switches
  1. "Design of an ATM Switch for Handoff-Support"
    H. Kim and H. J. Chao
    ACM/Baltzer Wireless network Journal (WINET), vol. 6, no. 6, pp. 411-419, Dec. 2000.

  2. "Design of a mobility-support ATM switch"
    H. Kim and H. J. Chao
    IEEE Global Telecommunications Conference (GLOBECOM), vol. 3, pp. 1408-1413, Nov. 1998

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Load Balanced Switches
  1. "Design and Performance Analysis of A Practical Load-Balanced Switch"
    Y. Shen, S. Panwar, and H. J. Chao
    IEEE Transactions on Communications. to appear in IEEE Transactions

  2. "Performance Analysis of a Practical Load-balanced Switch"
    Y. Shen, S. Panwar, and H. J. Chao
    2007 IEEE Workshop on High Performance Switching and Routing,Brooklyn, NY May 2007, .

  3. "Performance analysis of a practical load balanced switch"
    Yanming Shen, S. S. Panwar and H. J. Chao
    Workshop on High Speed Switching and Routing (HPSR), pp. 6, Jun. 2006.

  4. "Byte-Focal: a practical load-balanced switch"
    Y. Shen, S. Jiang, S. S. Panwar, and H. J. Chao
    IEEE Workshop on High Performance Switching and Routing, Hong Kong, May 2005.

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